The invention relates generally to computer systems. In particular, the invention relates to the sharing of an interrupt level by multiple interrupt sources.
A popular type of computer architecture allows multiple users to asynchronously request the service of a resource that is to be used exclusively by the source. One example of the resource is the processor and I/O channel of the computer system. Several I/O devices are attached to the I/O channel and have sufficient intelligence to execute tasks independently of the processor. However, at random times the I/O devices require communication with the processor. In this case, a request is sent to the processor requesting service by the processor. When the processor interrupts its own processing and honors the request, the details of the service request and possibly a response are conveyed on the I/O channel. It is, however, to be understood that the architecture associated with service requests and interrupt is more general than the situation just described.
One method of servicing these asynchronous requests for service is to have the processor periodically poll all the devices attached to the I/O channel to determine if the device requires service. This method though has several drawbacks. There is a high overhead associated with the polling because the poll must be periodically performed even if there are no outstanding requests. Furthermore, in order to reduce the overhead to a reasonable level, the repetition rate for the polling is made relatively long. As a result, though, the response to a service request becomes slow. In the usual situation, the I/O device making the service request cannot continue its own processing until the service request is serviced by the processor. As a result, system utilization falls with increased time between polls.
An alternative approach to polling is the use of interrupts or interrupt requests. A dedicated interrupt line is connected between the I/O device and the processor. Whenever the I/O device requires service, that I/O device outputs an interrupt signal onto the interrupt line. A separate interrupt terminal is provided on the processor and the processor, upon detecting an active interrupt line, goes into an interrupt servicing mode to service the request indicated by the interrupt signal. It should be emphasized that the interrupt signal is asynchronous with the operation of the processor and, indeed, is not necessarily synchronized with the processor clock if separate clocks are provided for the processor and the I/O device.
The computer architecture described above is satisfactory if there is only a single I/O device that is making interrupt request. However, it is more typical that there are several such I/O devices, each asynchronously requesting service by an interrupt signal. Indeed, the trend in modern computer architecture is for increasing intelligence contained in a large number of I/O devices. The communication to the processor, however, is performed over the I/O channel and requires the exclusive utilization of the processor and the I/O channel for the communication between the I/O device and the processor.
One conventional method of providing for multiple interrupt sources is to use a programmable interrupt controller. A popular programmable interrupt controller is the 8259 manufactured by the Intel Corporation and described in its publication "The 8086 Family Users Manual" dated October 1979 and available from the Intel Corporation in Santa Clara, Calif. This reference is incorporated herein by reference. The 8259 allows for eight interrupt levels. Each interrupt level has its own interrupt request line and the eight levels are prioritized among themselves. Whenever an interrupt request line indicates a request for service and the request does not conflict with a higher priority request, the 8259 outputs an interrupt signal on a single line to the processor that it supports. Along with the interrupt signal to the processor, the 8259 sends to the processor an interrupt vector associated with that interrupt level. The processor uses the interrupt vector to properly service the interrupt request.
For multiple interrupt sources, there is always the possibility that two interrupts for a service request are outstanding at a particular time. The 8259 prioritizes the outstanding requests and, possibly, the request currently being serviced. The highest priority request is serviced first, via the interrupt signal and interrupt vector to the processor, while the outstanding requests are held by the 8259. Thus, it is seen that the eight interrupt request lines to the 8259 function as separate interrupt levels. Apart from the prioritizing in the case of conflict, the eight different input levels are separable and each is operated similarly to the single interrupt level described above.
An important aspect of the use of the 8259 is the convention that an interrupt request signal to the 8259 transitions from a low to a high level to determine that an interrupt request has been received by the 8259. The convention further states that the interrupt request signal remains high until the request indicated by the interrupt has been serviced. It is a finite time T.sub.ID after the above described transition that the interrupt request line having the upward transition is measured to determine that it is still high. This measurement indicates which of the interrupt levels are currently asserted. It is to be noted that this high level measurement is redundant.
A single 8259 is thus designed to interface the interrupt request line for up to eight I/O devices. However, for modern computer systems this number turns out to be inadequate. For example, the Personal Computer (PC) of the IBM Corporation uses an 8259 as an interface for the interrupt request lines from the various additional boards plugged into the system or planar board housing the processor. Two of the eight interrupt request lines are, however, used for interrupts originating from the system board. The remaining six interrupt levels are lead to a bus connected to all the slots for additional I/O devices. Thus, there are an insufficient number of interrupt levels for a PC whose I/O slots are completely filled. In fact, some boards require more than one interrupt level. The problem is even worse because a particular board needs to be identified with a particular interrupt level. there are a large number of I/O boards, well in excess of six varieties, and the selection of the particular boards for a PC depends upon the user's needs. If the I/O boards are hard-wired for a particular interrupt level, the possibility arises that the selection of I/O boards is such that a large number of them are using the same interrupt level.
It would be possible, of course, to expand the number of interrupt levels, even with the continued use of the 8259. For instance, two or more 8259s can be used, as described in the previously cited Intel publication and also by Khera in U.S. Pat. No. 4,275,458. The difficulty with this approach is that it requires the number of interrupt lines that is equal to the number of interrupt levels. It is desirable to provide for additional interrupt sources without modifying the bus connecting the I/O slots to the system, that is, to continue with the use of only six interrupt levels.
It is possible to share an interrupt level, that is, that more than one interrupt source is somehow using the same interrupt level. In one version of the PC, the computer system can turn off the interrupt function on one or more boards. Thereby, two or more boards may be sharing an interrupt level but only one of them has an operable interrupt at any one time. This approach has the obvious disadvantage that some boards cannot always use their interrupt functions. Furthermore, its use depends upon the predictability of interrupts from particular boards. Such predictability is not assured and runs counter to the architecture of an interrupt driven system.
Another approach for interrupt level sharing is to provide the possibility of multiple boards outputting active interrupt level signals to a single interrupt request line and then to further provide software routines to determine which of the boards connected to that interrupt level is actually making the request. It is well known that TTL open-collector outputs can be used to share a single electrical line. Unfortunately, open collector outputs can assert a line only if the high level is non-asserted or inactive and the low level is asserted or active. Then, any low open-collector output will pull its connected line low regardless of the high output of any other open-collector output connected to that line. Such a convention is, unfortunately, inconsistent with the requirements of the 8259 which requires that the low state is inactive and the high state is active. A solution has been proposed by others to accommodate line sharing on the interrupt request inputs to the 8259. This circuit is illustrated in FIG. 1 in which the signal input to a tri-state buffer 10 is grounded. An enable input to the tri-state buffer 10 is connected to an internal interrupt signal 12. The output of the tri-state buffer 10 is connected to an external interrupt line 16 that has a pull-up resistor 14 to a voltage source equal to a high level for the logic circuit, for example, +5 V for TTL logic. When the tri-state buffer is not enabled, the pull-up resistor 14 pulls the output up to a high level, assuming that no other buffer connected to the external interrupt line 16 is pulling that line 16 low. However, when the tri-state buffer 10 is enabled by the internal interrupt signal, the output line 16 is grounded or put into the low state. The result can also be accomplished with an open-collector output of a TTL circuit.
Although it may appear that the negative pulse on the output line 16 has the wrong polarity for the 8259, in fact the 8259 responds to the positive transition 18 of the output signal and the output signal remains high following the positive transition to allow the identification of the interrupt level. Once the 8259 has detected the positive transition 18, it waits a time T.sub.ID before measuring the high level on the external interrupt line 16 to identify the interrupt level making the service request to the 8259. When that interrupt level is finally serviced, polling is performed by the system to determine which of the interrupt sources of that interrupt level has caused the interrupt.
There are several disadvantages to this approach. One of the most serious disadvantages is the possibility of a phantom interrupt. A phantom interrupt occurs when two interrupt sources of a particular level make closely timed interrupt requests as illustrated in FIG. 2. If the first interrupt source produces a negative pulse 20 on the external interrupt line 16 and then, in a time less than T.sub.ID following the upward transition 18, a second interrupt source produces a second negative pulse 22, when the 8259 measures the input levels on its interrupt request inputs, it detects a low or inactive level on the interrupt line 16 of this interrupt level. This situation of a measured low level following an upward transition on an interrupt request input does not conform to the convention for interrupts to an 8259. The 8259 is designed so that in such a situation, interrupt level 7 is indicated by default as the level requesting service even though this may not be the case.
The open-collector output approach has the further disadvantage that there may be two outstanding interrupt requests on the same external interrupt line. The second and subsequent requests are not explicity handled by the 8259. Once the positive transition 18 has been detected by the 8259, subsequent positive transitions have no effect until the 8259 recognizes the interrupt request on the interrupt line and forwards it to the processor. As a result, when the processor is responding to an interrupt request from a particular interrupt level, it is possible that more than one interrupt source of that interrupt level have an outstanding interrupt request. Thus the processor, once it has received an interrupt from the 8259, must poll every interrupt source of that level to determine which of them have outstanding requests. Furthermore, it is possible that the processor may be servicing one interrupt request on a particular interrupt level while a second interrupt source requests service. Thus, the only way that it is possible to determine that all outstanding interrupt requests on a particular interrupt level has been serviced is to not only poll each interrupt source of that level but to also to completely poll the sources of that level without finding an outstanding interrupt request. Needless to say, this approach exacts a high overhead for the processor.